Light emitting diodes (LEDs) are useful in various displays and especially in a new compact virtual display which utilizes an array of LEDs as an image source. The image source consists of a high pixel count (240 columns by 144 rows for a total of 34,560 pixels) 2-dimensional array of LEDs. The array of LEDs is used to form complete images containing pictorial (graphic) and/or alphanumeric characters. The complete images are then magnified to produce virtual images which appear to an operator to be at least the size of a standard sheet of paper.
One important factor in the quality of an image viewed on a given display, whether real or virtual, is the fill factor of the pixels within the emitting area. A high fill factor is desirable to obtain high quality images. For CRTs, the emission profiles of adjacent pixels actually overlap giving effective fill factors greater than unity, and producing a very smooth (not grainy) image. With matrix LED displays, however, it is not possible to achieve unity fill factors since there needs to be isolation between pixels. In addition, since conventional row/column matrix addressing schemes use metal row and column interconnects, there needs to be room for the column and row interconnect busses to pass through the pixel and to make contact to each electrode of the diode making up the pixel. For the columns, this interconnect component turns out to be the major component in the space required between pixels because of the minimum line width and alignment tolerances associated with this interconnect bus/contact processing.
In a copending application entitled "Electro-optic Integrated Circuit and Method of Fabrication", filed May. 9, 1994, Ser. No. 08/239,626, and assigned to the same assignee, a method of fabricating LED arrays is disclosed utilizing mesa etched processing technology. As can be seen in the figures of this copending application, one minimum dimension is needed for isolation, another for the column bus/cathode contact, and two alignment tolerances for placement of the metal. Generally, utilizing the present semiconductor fabrication techniques, 2 micron minimum line widths, spaces and alignment tolerances together with a 10 micron emission square for each diode give a minimum linear fill factor of 0.5 or an area fill factor of (0.5).sup.2 =0.25. The images produced by this display are somewhat grainy as a result of this relatively low fill factor.
Another problem faced in productizing the etched mesa LED arrays of the above describe copending application, at the present time, is the nonplanarity of the resulting structures. Efficient opto-electronic light emitters require relatively thick layers of epitaxial material grown on a substrate. Because of the relatively thick layers of epitaxially grown material, the mesa etching produces nonplanarities which tend to be on the order of 1 micron or greater. Such large nonplanarities can lead to problems with resolute photolithography, uniform dielectric coverage, metal step coverage, or metal column and row connectors.
Accordingly, it is highly desirable to provide methods of fabricating LED arrays which overcome these problems.
It is a purpose of the present invention to provide a new and improved method of fabricating LED arrays.
It is a further purpose of the present invention to provide a new and improved LED array with a substantially improved fill factor.
It is still a further purpose of the present invention to provide a new and improved method of fabricating LED arrays which is simpler and more efficient than prior methods and which is easily adaptable to high production levels.
It is another purpose of the present invention to provide a new and improved method of fabricating LED arrays which provides substantially planar semiconductor chips.